The present invention relates generally to memory devices and in particular the present invention relates to reading data from memory devices.
Memory devices are typically provided as internal storage areas in a computer, or processing system. The term memory identifies data storage that comes in the form of integrated circuit chips. There are several different types of memory. One type is RAM (random-access memory). This is typically used as main memory in a computer environment. RAM refers to read and write memory; that is, you can both write data into RAM and read data from RAM. This is in contrast to ROM, which permits you only to read data. Most RAM is volatile, which means that it requires a steady flow of electricity to maintain its contents. As soon as the power is turned off, whatever data was in RAM is lost.
Dynamic random access memories (DRAMs) are data storage devices that store data as a charge on a storage capacitor. A DRAM typically includes an array of memory cells that each include a storage capacitor and an access transistor for transferring charge to and from the storage capacitor. Each memory cell is addressed by a word line and accessed by a bit line. The word line controls the access transistor such that the access transistor controllably couples and decouples the storage capacitor to and from the bit line for writing and reading data to and from the memory cell. The data is read using a differential sensing circuit.
In a typical DRAM complementary bit lines are coupled to a differential sense amplifier. During operation, the bit lines are precharged and equilibrated to a common intermediate voltage. It is common to precharge the bit lines to xc2xd VCC prior to accessing a memory cell. The memory cell is then coupled to one of the bit lines and changes the voltage of the bit line. That is, the charge or lack of charge stored on the memory cell is shared with the charged bit line. The resultant charge will either be increased by a memory cell having a charge, or decreased by an unprogrammed memory cell. The differential voltage level between the complementary bit lines can then be detected and the respective bit lines amplified to either VCC or VSS.
The differential sensing scheme of the DRAM is fast and does not consume an unacceptable level of power. As such, differential sensing is used in different types of DRAM""s, including synchronous dynamic random access memory (SDRAM). An SDRAM is a type of DRAM that can run at much higher clock speeds than conventional DRAM memory. SDRAM synchronizes itself with a CPU""s bus and is capable of running at 100 MHZ, about three times faster than conventional FPM (Fast Page Mode) RAM, and about twice as fast EDO (Extended Data Output) DRAM and BEDO (Burst Extended Data Output) DRAM. SDRAM""s can be accessed quickly, but are volatile. Many computer systems are designed to operate using SDRAM, but would benefit from non-volatile memory.
Computers often contain a small amount of read-only memory (ROM) that holds instructions for starting up the computer. Unlike RAM, ROM cannot be written to. An EEPROM (electrically erasable programmable read-only memory) is a special type non-volatile ROM that can be erased by exposing it to an electrical charge. Like other types of ROM, EEPROM is traditionally not as fast as RAM. EEPROM comprise a large number of memory cells having electrically isolated gates (floating gates). Data is stored in the memory cells in the form of charge on the floating gates. Charge is transported to or removed from the floating gates by programming and erase operations, respectively.
Another type of non-volatile memory is a Flash memory. A Flash memory is a type of EEPROM that can be erased and reprogrammed in blocks instead of one byte at a time. A typical flash memory cell is fabricated in an integrated circuit substrate and includes a source region and a drain region that is spaced apart from the source region to form an intermediate channel region. A floating gate, typically made of doped polysilicon, is disposed over the channel region and is electrically isolated from the other cell elements by oxide. For example, gate oxide can be formed between the floating gate and the channel region. A control gate is located over the floating gate and can also be made of doped polysilicon. The control gate is electrically separated from the floating gate by another dielectric layer. Thus, the floating gate is xe2x80x9cfloatingxe2x80x9d in dielectric so that it is insulated from both the channel and the control gate.
Table 1 shows example approaches to programming, reading and erasing (two approaches) of a flash memory cell. The voltages are based upon the assumption that the primary supply voltage VCC for the memory is +5 volts. The conditions for programming call for the application of a high positive gate voltage Vg, such as +12 volts, a moderate positive drain voltage Vd of +6 to +9 volts, and the source voltage Vs and the substrate voltage Vsub are held at ground level.
The above conditions result in the inducement of hot electron injection in the channel region near the drain region of the memory cell. These high-energy electrons travel through the gate oxide towards the positive voltage present on the control gate and collect on the floating gate. These electrons remain on the floating gate and function to reduce the effective threshold voltage of the cell as compared to a cell which has not been programmed.
Table 1 also shows the conditions for reading the memory cell. Here, the control gate voltage Vg is connected to the primary supply voltage VCC of +5 volts. In addition, the drain voltage Vd is set to a small positive voltage of +1 volts and the source voltage Vs is set to ground potential. If the cell were in a programmed state, the excess electrons present on the floating gate would have increased the threshold voltage to a value in excess of +5 volts. Thus, the control gate Vg to source voltage Vs of +5 volts would not be sufficient to turn on the memory cell. That is, current would not be conducted through the channel region. The resultant lack of cell current would indicate that the memory cell was in a programmed state. If the memory cell were in an erased state, the threshold voltage of the cell would be substantially below +5 volts. In that case, the cell would conduct current in response to the control gate voltage that would be sensed to indicate that the cell was in the erased state.
Two exemplary conventional alternative sets of conditions for erasing a flash cell are shown in Table 1. In the first example, the control gate voltage Vg is grounded and the drain region is left floating (open), and the source region voltage Vs is connected to a large positive voltage of +12 volts. When these conditions are applied to the cell, a strong electric field is generated between the floating gate and the source region. This field causes the electrons on the floating gate to be transferred to the source region by way of Fowler-Nordheim tunneling, sometimes called cold electron injection.
The above conditions for erasing a cell have been viewed by others as disadvantageous in that the large positive voltage (+12 volts) applied to the source region is difficult to implement in an actual memory system. In another approach, a relatively large negative voltage ranging from xe2x88x9210 to xe2x88x9217 volts is applied to the gate during an erase operation. In addition, the primary supply voltage VCC of +5 volts (or less) is applied to the source region while the drain region is left floating.
In contrast to dynamic memory cells, a floating gate memory cell is typically read using a reference cell current. That is, a reference non-volatile memory cell is coupled to a current sensing circuit via a reference bit line. The read memory cell is coupled to the sensing circuitry via a second bit line. A differential current between the two bit lines is detected, and the programmed state of the memory cell is determined. The reference cell is typically programmed to an intermediate state such that it conducts about xc2xd the current conducted by a fully programmed memory cell.
While the current sensing technique using a reference current cell is effective for reading a small number of memory cells at one time, such as 8, 16 or 32 cells, the overhead involved in implementing this technique to simultaneous read a page of memory cells (e.g. 4 k memory cells) is too large. Further, maintaining the accuracy of the reference cell currents for reading a large number of cells is difficult, the speed of a current sensing technique is less than desirable, and the power consumption can be prohibitive.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a different method of reading data from memory cells.
The above-mentioned problems with non-volatile memory devices and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
A memory, in one embodiment, comprises an array of memory cells, a differential voltage sensing circuit having first and second sensing nodes couplable to the array, and pre-charge circuitry. Control circuitry is coupled to the pre-charge circuitry to provide a first pre-charge voltage level on the first and second sensing nodes during a first operation stage, and change the first pre-charge voltage level on the first sensing node to a second pre-charge voltage level on a subsequent second operation stage. In one embodiment, the pre-charge circuitry comprises pull-down circuitry to discharge local bit lines, and pull-up circuitry to charge global bit lines. The control circuitry selectively couples a first pre-defined number of local bit lines to first and second global bit lines during the first operation stage, and then selectively couples an additional second pre-defined number of local bit lines to the first global bit line during the second operation stage.
In another embodiment, a method of operating a memory device is provided. The method includes pre-charging first and second sensing nodes of a differential voltage sensing circuit to a first voltage level during a first pre-charge cycle, and pre-charging the second sensing node of the differential voltage sensing circuit to a second voltage level that is less than the first voltage level during a second pre-charge cycle. The method includes providing a read signal to a memory cell coupled to the first sensing node, and discharging the first sensing node to a third voltage level that is less than the second voltage level if the memory cell is not programmed. Pre-charging the first and second sensing nodes can comprise coupling first and second bit lines charged to an upper supply voltage to a plurality of third bit lines discharged to ground potential. Pre-charging the second sensing node during the second pre-charge cycle can comprise coupling an additional number of the third bit lines discharged to ground potential to the second bit line during the second pre-charge cycle.